1. Field of the Invention
The present invention relates to an apparatus and method for programming non-volatile memory cells and, more particularly, to an apparatus and method for lowering the potential barrier across the source-to-well junction during the programming of non-volatile memory cells.
2. Description of the Related Art
A non-volatile memory cell is a semiconductor device that stores information even after power has been removed from the device. Two of the most common types of non-volatile memory cells are electrically-programmable read-only-memory (EPROM) cells and flash memory cells.
FIG. 1 shows a cross-sectional diagram that illustrates a conventional EPROM or flash memory cell 10. As shown in FIG. 1, cell 10 includes spaced-apart n+ source and drain regions 12 and 14 which are formed in a p-type semiconductor material 16 such as a well or a substrate.
In addition, cell 10 also includes a channel region 18 which is defined between source and drain regions 12 and 14, a layer of gate oxide 20 which is formed over channel region 18, and a floating gate 22 which is formed over gate oxide layer 20. Further, cell 10 additionally includes a layer of interpoly dielectric 24 which is formed over gate 22, and a control gate 26 which is formed over dielectric layer 24.
EPROM and flash memory cells are commonly programmed to store one bit of information as either a logic zero or a logic one. More recently, however, programming techniques have been developed which allow EPROM and flash memory cells to store two or more bits of information.
The advantages of programming a single cell to store two or more bits of information are obvious. If each memory cell, for example, can be programmed to store two bits of information as either a "00", "01", "10", or "11", then the density of an array can be doubled without changing the physical size of the array.
One of these multi-bit programming approaches, as disclosed in U.S. Pat. No. 5,511,021 to Bergemont et al., teaches that a single EPROM or flash memory cell can be programmed to store a plurality of logic levels by utilizing a corresponding plurality of control gate voltages, and by forward biasing the source-to-well junction.
EPROM and flash memory cells are conventionally programmed by applying a programming voltage to control gate 26 and a drain voltage to drain region 14, while source region 12 and well 16 are grounded. When the programming voltage is applied to control gate 26, a positive potential is induced on floating gate 24.
The positive potential on floating gate 24, in turn, attracts electrons to the surface of channel region 20 to form a channel 30, and also repels holes to form a depletion region 32. When the drain voltage is applied to drain region 14, an electric field is established between the source and drain regions 12 and 14 in channel region 30 and depletion region 32.
The electric field accelerates the electrons in channel 30 which forms "channel hot electrons". The positive potential of floating gate 24 attracts these channel hot electrons which penetrate gate oxide layer 22 and begin accumulating on floating gate 24, thereby raising the threshold voltage of the cell.
As taught by Bergemont, given a sufficient amount of time, the threshold voltage of a cell being programmed will converge to a stable value which is defined by the programming voltage applied to control gate 26. In addition, the threshold voltages are linearly related to the programming voltages. Thus, for example, programming voltages of zero, one, two, and three volts will produce threshold voltages of approximately two, three, four, and five volts, respectively. (See FIG. 7 of Bergemont).
To reduce the amount of time required to achieve these stable threshold voltages, the source-to-well junction is forward-biased by placing a negative voltage on source region 12. By forward biasing the source-to-well junction, increased numbers of electrons are injected into depletion region 32 of well 16. These electrons are also accelerated by the electric field which, in turn, causes the formation of well or substrate hot electrons. A portion of the substrate hot electrons are then injected onto floating gate 22.
Negative voltages are commonly placed on circuit nodes, such as source region 12, via external sources or on-board charge pumps. External sources, however, are typically not a favored approach as this requires the use of a pin on the external package to input the external voltage.
Thus, although both external sources and on-board charge pumps may be used to provide the negative voltage required to forward bias the junction, it is desirable to have other approaches for injecting electrons into the well.